Measured, not estimated

What the fleet actually does.

Every number on this page is a real device benchmark, run in-cluster from the control plane. No projections, no marketing math. Where something isn't built yet, we say so.

Benchmarked 2026-09-24 · FP16 8192³ matmul · serving on Qwen2.5-7B (Q4), GPU-resident

Compute
~520 TFLOP/s
dense FP16, 12 GPUs
GPU memory
201 GB
across the fleet
GPUs online
12
in the fleet
Serving
~1,195 tok/s
9-GPU serving pool

The fleet, card by card

Three GPU architectures under one control plane. The eight Blackwell cards land within 1.5% of each other — the fabric, drivers, and cooling all behave identically.

TierCardsArchFP16VRAM
NVIDIA — workhorse8× RTX 5060 TiBlackwell (sm_120)~50 TFLOP/s ea16 GB ea
NVIDIA — Ada1× RTX 4060 TiAda (sm_89)45.8 TFLOP/s16 GB
AMD — modern1× RX 9060 XTRDNA4 (gfx1200)40.4 TFLOP/s16 GB
AMD — HBM22× Radeon Pro VIIgfx90615.5 + 16.6 TFLOP/s16 GB ea
Verified total · 12 GPUs~520 TFLOP/s201 GB

Serving throughput

Real token generation on a 7B (Q4) model, GPU-resident.

  • Single stream~85 tok/s
  • 4-way concurrent (per GPU)~130 tok/s
  • Prompt prefill>1,200 tok/s
  • Serving pool (9 GPUs)~1,195 tok/s
  • 123B (Mistral-Large-2) across the RPC pool (8 GPUs)~2.7 tok/s · benchmarked

Serving pool = 7 Blackwell + 1 Ada + 1 RDNA4 for fast 7B. The RX 9060 XT and both HBM2 Radeon Pro VII cards are now cluster-joinable as GPU peers via Vulkan (RADV) — folding the full fleet into one large-model pool.

What fits on one 16 GB card

  • FP16 (full precision)~7–8B
  • INT8 / FP8~13B
  • 4-bit (GPTQ/AWQ)~30B
  • 123B-class (RPC pool)benchmarked

Every worker clears the ~30B (4-bit) bar on one card; the NVIDIA tier does it eight times over, in parallel. 70B-class has been benchmarked across a cross-GPU llama.cpp RPC pool (5 GPUs, measured ~7 tok/s) over the 2.5 GbE fabric — modest speed, but real. Larger models are in active bring-up.

Many fast workers — and now one pooled large-model engine

The nodes are separate machines joined by a 2.5 GbE fabric. That's ideal for running many models side by side and serving many users in parallel — the fleet's real shape is 12 independent GPU endpoints, a throughput farm. Splitting one very large model across nodes is bottlenecked by the network, not the silicon; we shipped exactly that engineering path — a llama.cpp RPC pool (CUDA + Vulkan) that now serves 70B-class live at modest, honest tok/s. Two real shapes: a throughput farm of independent endpoints, and one pooled large-model engine.

Method & caveats

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